This invention relates to a method of manufacturing a trench-gate semiconductor device of the type comprising a semiconductor body having a plurality of transistor cells, each transistor cell being surrounded by a trench-gate comprising a trench extending into the semiconductor body with gate material in the trench, and each transistor cell having source and drain regions which are separated by a channel-accommodating region adjacent to the trench-gate. The invention also relates to semiconductor devices of this type manufactured by such a method.
In a method of manufacturing a trench-gate semiconductor device of the above-defined type which is known from WO-A-99/54918 (our reference PHB34245), the method includes the steps of:
(a) forming at a surface of the semiconductor body a first mask of a first material having first windows, each first window having a mid-point path coincident with a mid-point path of a said trench which will be formed later;
(b) forming on the semiconductor body a second mask having second windows, each second window being formed within and smaller than a said first window by providing two sidewall extensions to the first mask in the first window; and
(c) forming said trenches by etching into the semiconductor body at the second windows.
In the disclosed method of WO-A-99/54918 the above-stated steps (a), (b) and (c) are included in making the semiconductor device as a vertical power transistor by a self-alignment process which enables a reproducible transistor cell pitch of 5 xcexcm or less. The width of the trench-gate trenches is not discussed, but in this disclosed method the two sidewall extensions to the first mask which form each second window each have a curved sidewall. During etching of the trenches the width of these sidewall extensions will reduce due to their curved sidewall surface. Thus the second windows and hence the trenches will be widened during trench etching.
An object of the present invention is to provide a method which is better adapted for producing narrow trenches in a trench-gate semiconductor device.
According to the present invention there is provided a method as defined in claim 1, that is a method including steps (a), (b) and (c) as above-defined, the method being characterised by the steps of:
(d) providing in each first window a continuous layer of a second material from which the second mask will be formed, the layer of second material having upright portions on the sidewalls of the first mask and a base portion on the surface of the semiconductor body;
(e) forming an intermediate mask of a third material in each first window covering the upright portions of the layer of second material and covering the base portion of the layer of second material except where the second window will be formed;
(f) using the intermediate mask in each first window to etch the base portion of said layer of second material and form said second window; and
(g) removing the intermediate mask to leave a pair of L-shaped parts of said second material within each first window as said two sidewall extensions to the first mask, each L-shaped part having a rectangular section base portion with a top surface parallel to the semiconductor body surface and a side surface perpendicular to the semiconductor body surface, and then carrying out step (c) to form said trenches.
In the method of the present invention, the rectangular section base portion of each L-shaped part ensures that there is no appreciable widening of the second windows during trench etching. The trenches will be uniformly vertically etched and will be maintained narrow during etching in accordance with the second windows defined by the L-shaped parts.
JP-A-09134916 discloses a method of manufacturing a semiconductor device including steps similar to the above-stated known steps (a), (b) and (c) of the present invention except that the second windows are not used for etching trench-gate device trenches but are instead used for etching shallow grooves which will accommodate recessed local oxidation isolation regions. The sidewall extensions provided to the first mask for forming the second windows are disclosed in one embodiment of this document as parts having a curved sidewall and are disclosed in another embodiment as L-shaped parts. The choice between these two types of sidewall extensions which is made in the method of the present invention for the purpose of better production of narrow trench-gate device trenches is not derivable from the teachings of this document JP-A-09134916.
Preferred features of the method in accordance with the present invention, including features adapted to the method being for manufacturing the semiconductor device as a vertical power transistor and features adapted to the method being for manufacturing the semiconductor device as a memory device, are defined in claims 2 to 15. A trench-gate power transistor manufactured by the method of the invention and preferred features of such a power transistor are defined in claims 16 to 19. A memory device manufactured by the method of the invention is defined in claim 20. Advantages of the just-mentioned preferred features are discussed in relation to the embodiments described below.